SVE - Simulation and Verification Environment
The Simulation and Verification Environment (SVE) is a complete end-to-end simulation and verification tool for Mercury FPGA-based systems, designed to enable application developers to quickly model and verify application logic, dramatically reducing time to market. The SVE architecture is based upon the OVM open-standard verification methodology (Open Verification Methodology, ovmworld.org). It is designed to allow users to quickly simulate and verify new designs, reducing verification time by up to 60-70% by providing complete verification infrastructure, integrated fabric, Bus Functional Models, and a library of pre-built tests with a unified easy-to-use API. This highly configurable, comprehensive solution is designed to test the FPGA and all its interfaces at the system level by emulating real-world traffic scenarios with a selectable degree of randomness.
Features
- Compliance with industry-standard System Verilog-based OVM environment
- Concurrent operation of various number and types of interfaces with synchronization between them
- Programmable data/traffic generation and response checking
- Error insertion/detection
- Code and functional coverage as a measure of completeness
- Configurable symbol or bit serial interface
- Library of pre-built directed, constrained random, and performance test cases for testing of specific functionality and detecting corner cases
- Directed, constrained-random performance tests using a unified API
- Sparse memory for Bus Functional Models
- Deposit of data files in memories at time 0
- Serial interfaces that can run in parallel mode to improve simulation time
Benefits
- Simulation and verification tool for Mercury’s FPGA systems
- Simulates and verifies FPGA-based application designs
- Dramatically reduces time to market
- Supports all external board interfaces
- Integrates fabric interfaces (SRIO, PCIE, 10GE) seamlessly with unified easy-to-use APIs
- Domain knowledge-developed and deployed by system and application experts
Specifications
Language
System Verilog HDL OVM
Supported platforms and simulators
Mentor®/Cadence®
Supported switch fabrics
PCI Express®, RapidIO®, XAUI, 10GE
Symbol interface: 10 bit
1x and 4x serial interfaces
Scoreboard port
Synchronization between various interfaces
Input/output and message-passing protocols
All transaction flows and priorities Product Options
Single or multi-use license Compliance
RapidIO specification, Revision 1.2
PCI Eexpress specification, Revision 1.1 Prerequisite Product
Mentor Questa Sim Verilog/VHDL and Synplicity Verilog/VHDL
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