Language: Verilog® HDL
Synthesis: Synopsys®/Synplicity®/Altera®
IC technology
0.13 micron or better ASIC; Stratix® IV or
Xilinx® v5, v6 FPGA
Simulation: Mentor QuestaSim/OVM
Support for:
Serial specification: 1.2 GHz, 2.5 GHz, 3.125 GHz, 5 GHz
4x serial interfaces
34-bit addressing
NWRITE, MAILBOX, and CFG operations
All legal data payload sizes up to 256 bytes
Availability and Serviceability
Available now
Product OptionsSingle or multi-use license
Soft IP core: RTL source code, synthesis scripts, and so on
Comprehensive documentation package
Compliance
RapidIO Specification, Rev. 2.1 (5 GHz short control symbol)