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Serial RapidIO IP Core

Serial RapidIO IP Core is a high-performance solution that is independent of physical layer designs, implementation tools, and target technology. It is capable of addressing a variety of solutions, including endpoint and switching applications. The core is designed for the growing RapidIO market.

The RapidIO Interconnect Architecture is an industry-standard, high-performance, packet-based interconnect technology that provides a high-speed interconnect between NPUs, CPUs, and DSPs. It addresses the need for a standards-based, high-speed, reliable interconnect and is targeted at the networking, embedded, and storage markets. Serial RapidIO allows chip-to-chip, board-to-board, and system-to-system communications scaling to 10 Gbps and beyond.

  • Industry-standard, high-performance, packet-based interconnect technology
  • Provides both RapidIO endpoint and switch applications
  • Implements an advanced buffer management scheme
  • Targets both FPGA and standard cell technologies
  • Scales to 10 Gbps and beyond
  • High-performance, high-function core
  • Ideal for use in a variety of high-end embedded compute applications
  • Simplifies the construction of add-on third-party bus interfaces

Language: Verilog HDL
Synthesis: Synopsys®/Synplicity®
Technology: 0.13 or better and FPGA
Simulation: Model Technology

Support for:  Serial specification 1.2 GHz, 2.5 GHz, 3.125 GHz
  1x and 4x serial interfaces
  Error management extensions
  34-bit addressing
  All legal data payload sizes up to 256 bytes
  Input/output and message-passing protocols
  Receiver-controlled and transmitter-based flow control
  All transaction flows and priorities
  Multicast event support

Availability and Serviceability
  Available now

Product Options  Single or multi-use license
  Soft IP core: RTL source code, synthesis scripts, etc.
  Comprehensive documentation package

Compliance  RapidIO specification, Revision 1.2

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