Echotek Series DCM-V5-VXS
Virtex-5 Based FPGA Digital Receiver

• Three Xilinx Virtex-5 SX240T or LX330T FPGAs for processing and I/O interfacing
• High-speed VXS or RACE++ interface on backplane
• Two QSFP fiber interfaces
• DDR2 SDRAM and QDR2 SRAM memory
• SecureConfig with options to load FPGA images to either non-volatile flash or DDR2 SDRAM (volatile)

• High-performance Virtex-5 FPGA-based A/D conversion
• Industry-leading signal integrity as measured by SNR, SFDR, and SINAD
• Ultimate processing power utilizing three Xilinx® Virtex-5 SX240Ts or LX330Ts
• Flexible A/D conversion via two FMC sites
• High-speed fiber connectivity via the front panel
• High-speed VXS interface or RACE++® interface

FPGAs  
2 Prosecutor FPGAs 
      Xilinx Virtex-5 SX240T or Xilinx Virtex-5 LX330T
1 Governor FPGA
      Xilinx Virtex-5 SX240T or Xilinx Virtex-5 LX330T

MemoryDDR2 SDRAM: 3 banks
   One bank: 256 MB
QDR2 SRAM: 3 banks
   One bank: 9 MB

Data Paths
FMC 1 to Prosecutor 1
   80 LVDS pairs at up to 1 Gb/s per pair
   10 GTP lanes at up to 3.125 Gb/s per lane
FMC 2 to Prosecutor 2
   80 LVDS pairs at up to 1 Gb/s per link  
   10 GTP lanes at up to 3.125 Gb/s per lane
Prosecutor FPGA 1 to QSFP 1
   4 GTP lanes at up to 3.125 Gb/s per lane
Prosecutor FPGA 2 to QSFP 2
   4 GTP lanes at up to 3.125 Gb/s per lane
Prosecutor FPGA 1 to Prosecutor FPGA 2
   Dual 16 full-duplex HSDL links at up to 4 GB/s
Prosecutor FPGA 1 to Governor FPGA
   16 full-duplex HSDL links at up to 2 GB/s
   8 full-duplex HDSL links at up to 1 GB/s
   8 GTP lanes at up to 3.125 Gb/s per lane
Prosecutor FPGA 2 to Governor FPGA
   16 full-duplex HSDL links at up to 2 GB/s
   8 full-duplex HDSL links at up to 1 GB/s
   8 GTP lanes at up to 3.125 Gb/s per lane

Environmental
Temperature
   Operating: 0ºC to 40ºC with 300 LFM of airflow
    Storage: -40ºC to +85ºC

Ruggedization Level VHConduction-cooled: Consult factory.