Specifications
Cell BE Processor
PPE core: IBM® 64-bit Power Architecture™
L1 cache size: 32 KB instruction; 32 KB data
L2 cache size: 512 KB
SPEs: 8
Local store: 256 KB
Registers: 128 x 128 bits wide
EIB: 180 GB/s sustained aggregate bandwidth
Processor internal clock speed: 2.8 GHz
Processor-to-memory bandwidth: 22.8 GB/s
Memory
CBE: 4 GB DDR2 DRAM, 2 DDR2 channels, 1 Gb x 8
ECC support: Single-bit correct; double-bit detect
Flash: 2x16 MB
Companion chip: 256 MB, 2 channels each, 512 MB x 16
Cell Accelerator Board 2 Software
Cell 64-bit Linux® operating system and drivers
Linux and Windows® XP64 drivers for host
In host operation
Operates with customer-supplied Windows XP64
or 64-bit Linux operating system.
Host Cross Tool Chain for development for Cell PPE and SPE
MultiCore Plus™ Cell SDK Software (Optional)
(32/64-bit application support)
MCF (MultiCore Framework): PPE/SPE
TATL™ (Trace Analysis Tool and Library): PPE/SPE
SAL (Scientific Algorithm Library): PPE/SPE
MultiCore SAL SPE: PPE/SPE
PixL™ (Image Processing Algorithm Library): PPE
SPEAD-K (SPE Assembly Development Kit): SPE
Size
Length: 312 mm (12.283 in)
Width: 40.64 mm (1.6 in)
Height: 113.15 mm (4.455 in)
The board dimensions are compatible with the PCI Express x16 Graphics 150W-ATX Specification 1.0.
Environmental
Ambient temperature: 5°C to 35°C
Humidity: 5-85% non-condensing
Altitude
3000 ft at 35°C
7000 ft at 32°C
Power
Cell Accelerator Board 2 with 4-GB DDR2: 150W
Power is provided through the use of a single cable connector in addition to the 75W power provided through the PCI Express edge connector.
Qualified Chassis/Environments
Consult your Mercury sales representative for information on qualified chassis and environments.
Compliance
Safety: UL/CSA 60950-1 and IEC/EN 60950-1
EMC: EN 55022, EN 55024:1998
European Directive 2002/95/EC (RoHS Directive)
FCC Part 15 Class A
ICES/NMB-003 Class/Classe A